Verilog

Verilog HDL design of frequency divider in RTC module is studied here.

文中研究在RTC模块中分频器设计的VerilogHDL实现.

Manchester codec Verilog code very good speed, but also occupy less resources.

曼彻斯特编解码Verilog代码非常好的速度快, 而且资源占用少.

This design realizes with verilog hardware describing language, so it has a good flexibility and portability.

本设计采用Verilog硬件描述语言实现, 具有良好的可移植性和设计灵活性.

ARM 7 _ verilog source code, after commissioning, is pretty good.

ARM7_verilog的源代码, 经过调试, 很不错.

The function of circuit was verified by Verilog-XL.

整个电路的功能通过了Verilog-XL 的仿真.

UART Receiver Verilog Code complete code can be used directly.

异步接收器Verilog代码完整的源代码可以直接使用.

Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code, through simulation.

通用串行异步收发器8251的VerilogHDL源代码, 经过仿真验证.