Logic block packing is the last procedure of FPGA technology mapping.

An FPGA is a chip that consists of many unconfigured logic gates.

FPGA是一种包含许多未配置逻辑门的芯片.

This paper introduces a FPGA-based TFT-LCD display controller design and implementation methods.

文章介绍了一种基于FPGA的TFT-LCD显示控制器的设计和实现方法.

Responsibility: 1. Design high speed FPGA board for algorithm verification . 2.

工作职责: 1. 设计用于算法验证的高速FPGA板.

The FPGA implementation scheme of LPT is also discussed in the paper.

给出了对数极坐标变换的FPGA实现方案.

A trigger signal generator based on FPGA is introduced in this article.

介绍了一种基于可编程逻辑门阵列(FPGA)的脉冲触发信号发生器.

Finally this circuit verified by FPGA and the test result given.

最后,通过现场可编程门阵列(FPGA)验证,给出了测试结果.

The smoothly running of step motor can be implemented using FPGA.

用现场可编程门阵列(FPGA)实现步进电机平滑运行.

PVC construction with PTFE seat and FPM seals.

PVC结构,配置聚四氟乙烯阀座和FPM密封.

Replaceable FPM O-ring seats and seals.

可更换FPM材质的O形环阀座和密封.

" In this cold there are no fps around.

“ 天冷,拉不上座儿.

Danger: Slow or old computers will have FPS lag in Base Camp.

危险: 慢或旧电脑将在大本营医科滞后.

Moreover , the dynamic simulation data have fully validated the feasibility of the newly FPS scheme.

动模试验数据也充分验证了故障选相新方案的可行性.

The development and principle of FPS system is outlined.

本文对FPS系统 的发展及工作原理作了简单介绍.

Method: HPLC-FPS was used.

方法: 应用(HPLC-FPS)建立厚朴的指纹图谱.

It runs smoothly at 15 fps for 320 x 280 images on P 4 1.4 GHz PC.

当视频输入大小是320×280,每秒15帧;该系统可以平滑地在P41.4GHZ的计算机上运行.

The video runs smoothly and due to the little screen the low FPS is barely noticed.

视频播放平滑顺畅,而且归于较小的屏幕,低FPS几乎注意不到.

The tool preference was FPS-R 48.1 %, NRS 24.4 % , YDS 23.1 % and VAS 3.8 %, respectively.

工具首选率依次为FPS一R48.1% 、 NRS24.4% 、 VDS23.1%和VAS3.8%.

But it is variable during the motion of the FPS slider.

然而,实际上FPS支座 的滑动摩擦系数在FPS滑 块的运动过程中是变化的.

Our H .264 encoder isoptimized to provide 15-25 fps encoding performance for QCIF resolution video.

我们的H.264编码器每秒钟可以编码帧15至25帧QCIF图像.

Some may socialize by joining an FPS clan and compete in ladders and tournaments.

一些玩家喜欢加入FPS的战队,一起过关.