pll

Working knowledge of clock synchronization using phase-lock loop ( PLL ).

理解用锁相环 ( PLL ) 实现时钟同步.

Motor stator flux observer based on PLL was studied further.

对一种基于锁相环原理的电机定子磁链观测器作进一步研究.

PLL frequency synthesizer based on fractional frequency division and ∑-� � technique is introduced.

本文介绍了采用 ∑- △调制技术的小数分频PLL频率合成器.

The ICO, modulator, transmitter, PLL, time-domain filter in the modem are also deeply discussed.

本文还对调制解调电路中的ICO 、 调制器 、 发送器 、 PLL 、 时域滤波器作了细致探讨.

The phase jitter of output signal of the PLL ( phase locked loop ) frequency doubler is analyzed.

定量分析了数字式锁相 倍频器 输出信号的相位抖动.

PLL frequency synthesizer with DDS reference will adapt to local oscillator of modern radio.

采用DDS输出作为参考的PLL频率合成器非常适合用做现代电台的本振.

The transistor-level closed-loop simulation demonstrates the stable operation of the designed PLL.

最后在电晶体等级的 闭路 模拟中可得知所设计的锁相回路有著稳定的表现.

Outputs serial data transferred from the PLL to the controller.

从PLL输出串行信号到控制器.

A fast locking phase-locked loops ( PLL ) with a dual-slope phase frequency detector circuit is presented.

文中提出了一种用于高速锁相环的双斜鉴频鉴相器的结构设计.

Therefore , the research of low noise PLL design a very hot topicand of value.

如何减小锁相环路的噪声(时域中称为抖动)是设计者们研究的热门方向.

The basic theories of the frequency synthesis , PLL , DDS, DDS + PLL are introduced first in this paper.

本文首先介绍了关于频率合成、锁相环频率合成、DDS频率 合成 、 DDS+PLL频率合成等的基本理论.

PLL is used for generating carry synchronization signal.

采用平方环实现载波同步信号的提取.

The power consumption due to PLL itself is exclude.

电源损耗由于PLL自身而被排除.

VCO is the major contributor of the PLL output noise.

压控振荡器是锁相环噪声的主要来源.

High stability PLL-modulator and high sensitivity receiving demodulator are introduced.

介绍了高稳定锁相调制和高灵敏度的接收解调.