design-for-testability

As a standard technique of test and Design-For-Testability for testing the digital printed circuit board, Boundary-Scan technique has obtained widespread application in electronic equipment.

边界扫描技术是一种标准的数字电路测试及可测试性设计方法，它在工业界得到了广泛的应用。

For the logic part, the single cell fault model is assumed and novel design-for-testability techniques are applied.

逻辑模块采用了新颖的可测性设计方法，假设了单元故障模型。

Design-for-testability of analog and mixed-signal IC

模拟及混合信号芯片的可测性设计

Design-for-Testability and Test Technologies for System-on-a-Chip

SOC可测试性设计与测试技术

Novel Optimum Identification for Analog Design-for-Testability ( DfT) Comes from Fast Convergence Identification As RBF is publicly recognized as having good astringency, fast convergence speed and stability of computation, the author attempted to develop an RBF-based optimization algorithm for designing the FIR digital filters.

由于公认为径向基函数网络具有好的收敛性与收敛速度，并且在计算稳定性方面也具有相当好的性能，作者将径向基函数网络的优化算法应用于FIR数字滤波器的设计中。

Design-For-Testability, DFT has become a very important part of the CMOS chip and system design.

可测试性设计（Design-For-Testability，DFT）已经成为芯片或系统设计中不可或缺的重要组成部分。

Test and Design-for-Testability of IIR Filter

IIR滤波器的测试及可测性设计

Structural design-for-testability of accumulation-based testing for DSP data path

DSP数据通路基于累加器测试的结构可测性设计

Boundary scan testing based on design-for-testability is a new method to test VLSI. This method can greatly reduce the complexity of VLSI test generation, so it has been studied extensively in the fields of design and test of integrated circuit in recent years.

边缘扫描测试是对大规模集成电路（VLSI）进行测试的一种新的基于可测性设计的测试技术，能极大地降低VLSI测试生成的复杂性，在电路设计与测试领域，近年来得到广泛关注。

Improvement of testability: For the purpose of reducing test cost and obtaining higher fault coverage, several Design-for-Testability ( DFT) methodologies of the circuit are concerned.

可测性的改善。为了降低测试成本和提高故障覆盖率，必须对原芯核电路进行可测性设计，为此本文研究了几种用以提高电路可测性的措施。

Low Power MP3 Decoder and Its Design-for-Testability Techniques

低功耗MP3解码器设计及其可测性分析

The Design-for-Testability ( DFT) technique is a good method to solve test problem.

解决测试问题的一个好办法是使用可测性设计。

Based on arithmetic additive generator, we present an universal design-for-testability and test strategy for infinite impulse response ( IIR) filter.

基于加法器测试生成，提出了无限脉冲响应（IIR）滤波器的一种通用可测性设计、测试方案。

Arithmetic test and design-for-testability for FFT processor

FFT处理器的算术测试与可测性设计